At present, the development speed of networks is amazing. Due to growing of network flow and constant emerging of new services, network equipment needs to have quick and flexible processing capacities, which raises higher requirements on the performance of a core of the network equipment, i.e. a network chip (such as, a Network Processor (NP)). Generally, a great variety of counters, which are configured to implement port statistics, flow statistics and the like, are set in the network chip. Each item of a counter defines a certain amount of BITs, the width of which determines a maximum value of the counter, for example, the maximum value of the counter is 1023 if 10 BITs are provided, the value is overflowed and reversed and the counting is carried out from 0 if the maximum value is exceeded.
Currently, a usually adopted method of preventing the counting overflow of a counter of a network chip is: a drive periodically polls counting values of a counter by virtue of a timer and constantly collects sample values of the counting values, and if a sample value reaches a threshold, an upper-layer drive records the sampling value, and resets the counter to count starting from 0.
However, the defects of the counting way are that a processor needs to constantly sample the counter which causes great computational burden on the processor.